Forward Error Correction

Error detection and correction codes are used nowadays in almost any digital transmission and storage system to ensure reliable transfer of information.

Noesis Technologies offers a complete portfolio of forward error correction IP cores including Reed-Solomon, Viterbi, BCH, LDPC and Turbo Product codecs. These state-of-the-art hardware implementations have established Noesis Technologies as a worldwide leading provider in FEC IP core solutions. Noesis Technologies forward error correction IPs are developed to boost performance in wireless LANs and Internet, satellite communications, wireless broadband systems, optical networking, wireline access networks, data storage as well as in a variety of other target applications that require error detection and correction techniques.

Noesis FEC solutions are highly configurable, with optimized architectures that can be targeted to multiple wireless or wired standards and can meet the most demanding area and speed application requirements. All of the FEC IP cores are silicon proven (FPGA or ASIC) and technology independent for easy and risk-free porting to any target silicon process.