ASIC/FPGA Design Engineer

Three years experience in digital design and verfication. Very good VHDL or Verilog and C or C++ coding experience is essential. Experience in DSP algorithm development is a plus.
Please email your resume at
careers@noesis-tech.com.

Senior DSP Engineer

At least 10 years experience in developing and optimizing SW for DSPs. C or C++ programming experience. In depth knowledge of DSP architectures.
Please email your resume at
careers@noesis-tech.com.


Please no agencies.
Careers
Copyright 2012 Noesis Technologies L.P. All rights reserved. | Terms Of Use | Privacy Policy | Sitemap