ASIC/FPGA Design Engineer

Three years experience in digital design and verfication. Very good VHDL or Verilog and C or C++ coding experience is essential. Experience in DSP algorithm development is a plus.
Please email your resume at

Senior DSP Engineer

At least 10 years experience in developing and optimizing SW for DSPs. C or C++ programming experience. In depth knowledge of DSP architectures.
Please email your resume at

Please no agencies.
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