Low Density Parity Check (LDPC) Codes
IEEE 802.11 n/ac/ac LDPC Decoder - ntLDPCD_80211
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_80211 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity.
The ntLDPC_80211 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_80211 decoder IP (Figure 2) implements a 81-bit parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=27,54 or 81 expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The ntLDPC_80211 cores can be used in a variety of applications, including:
- IEEE 802.11 n/ac/ax Wi-Fi 4, 5 or 6 standard compliant cases.
- Custom state-of-the-art systems for efficient high throughput FEC protection in both wire-line or wireless types of applications.
- Decoder supporting all IEEE 802.11 n/ac/ax defined block lengths (648, 1296, 1944) and code rates (1/2, 2/3, 3/4 and 5/6).
- Soft input decoder interface wrapper with 4(S4.0), 5(S5.0, S5.1) or 6(S6.0, S6.1, S6.2) bit LLRs support and 27*LLR or 81*LLR parallelism.
- Automatic scaling of internal fixed point precision according to selected input fixed point precision.
- Flexible generic decoder architecture with various combinations of parallelism options providing any desired application trade-off between area, performance and throughput rates.
- Maximum internal parallelism level of 81 parallel LLRs processing for high throughput applications.
- Programmable number of algorithmic iterations.
- Programmable Early Termination feature, with layered parity check criterion, for substantial throughput rate increase, without any measurable performance loss.
- Probe outputs returning the number of actual performed decoding iterations per frame for quality statistics extraction.
- Generic selection of multiple encoder/decoder instances under the same top level IO interface for seamless throughput increase.
- Peak data rate > 4Gbps, measured on Xilinx RFSoC FPGA, with ~10% device utilization. Higher rates achievable for FPGA or ASIC technologies.
- Synchronous single clock design.
- Silicon proven in ASIC and Xilinx FPGA implementation technologies.
The ntLDPC_80211 decoder core has been synthesized using Xilinx Vivado software. The core has been targeted to Ultra Scale RFSoC xczu28dr-ffvg1517-2-e FPGA device with a default balanced optimization strategy between area and timing. The area and performance metrics produced are summarized in the following tables.
| Description | Decoder P=81// IF 1x processing IP S4.0 LNOMS | Decoder P=27// IF 1x processing IP S4.0 LNOMS | Decoder P=81// IF 2x processing IP S4.0 LNOMS | Decoder P=81// IF 3x processing IP S4.0 LNOMS |
|---|---|---|---|---|
| FF | 7787 (0.92%) | 7789 (0.92%) | 15126 (1.78%) | 22447 (2.64%) |
| LUT | 15654 (3.68%) | 15524 (3.65%) | 31021 (7.29%) | 45243 (10.64%) |
| BRAM | 34 (3.15%) | 34 (3.15%) | 63.5 (5.88%) | 93 (8.61%) |
| MHz | 350 MHz | 350 MHz | 330 MHz | 310 MHz |
In the IP Core product brief we present performance metrics of BER vs. ES/N0, throughput rates and relative average iterations for BPSK modulation as measured in real-time using Noesis ComLab SW platform running at RFSoC FPGA.
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntLDPC_80211 core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies).
The following deliverables are included:
- Fully commented synthesizable VHDL source code or FPGA netlist.
- VHDL test bench and example configuration files.
- MATLAB model.
- Comprehensive technical documentation.
- Technical support.
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.
