Digital Video Broadcasting (DVB)


The ntDVBS2_FEC transmitter and receiver IPs, each instantiate a BCH and LDPC concatenated pair of encoders and decoders respectively. The ntBCH_DVBS2 encoder (Fig.1) performs BCH encoding to payload frames by appending calculated parity bits at the end of each frame. The ntBCH_DVBS2 decoder (Fig.2) finds the error locations within a received frame, tries to correct them and indicates a successful or failed decoding procedure. The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_DVBS2 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity.


The ntLDPC_DVBS2 encoder IP (Figure 1) implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling MATLAB script processes the original IRA matrices and produces a set of constants, associated with the matrix and hardcoded in the RTL encoder. Encoding is performed as a three part recursive computation process, where row sums, checksums of all rows column-wise and parity bit sums are calculated. The ntLDPC_DVBS2 decoder IP (Figure 2) implements an approximation of the log-domain LDPC iterative decoding algorithm (Belief propagation), known as Layered Lambda-min2 Algorithm. The core is highly reconfigurable in terms of area, throughput and error correction performance trade-offs and is fully compliant to the DVB-S2 standard. Two highly complex off-line pre-processing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2 decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. Two separate off-line profiling MATLAB series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360×360 shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features two powerful optional early termination (ET) criteria (convergence and parity check), to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.

The ntDVBS2_FEC cores can be used in a variety of applications, including:

  • Digital Video Broadcasting DVB-S2.
  • Custom state-of-the-art systems for Optical transmission systems, Satellite Communication Systems or Deep Space high data rate applications.
  • Transmitter and Receiver, support all DVB-S2 defined block lengths [16200,64800] and code rates [1/4,1/3,…,8/9,9/10].
  • 9-Bit or 360-Bit transmitter input/output interface wrappers, supporting AXI4 Lite bus protocol.
  • Soft input decoder interface wrapper with 4(S4.0), 5(S5.0, S5.1) or 6(S6.0, S6.1, S6.2) bit LLRs support and 9*LLR or 360*LLR parallelism. Optional AXI4 Lite bus protocol support.
  • Automatic scaling of internal fixed point precision according to selected input fixed point precision.
  • Flexible generic decoder architecture with various combinations of parallelism options providing any desired application trade-off between area, performance and throughput rates.
  • Configurable internal 360/180 DPUs parallel LLRs processing for high throughput applications.
  • ntDVBS2_FEC receiver achieves competitive decoding performance results, meeting closely DVB-S2 Quasi Error Free requirements.
  • Programmable number of algorithmic iterations and Early Termination feature, with both convergence and layered parity check criteria, for substantial throughput rate increase, without any measurable performance loss.
  • Probe outputs returning the number of actual performed decoding iterations per frame for quality statistics extraction.
  • Synchronous single clock design.
  • Silicon proven in ASIC and Xilinx FPGA implementation technologies.

The ntDVBS2_FEC transmitter and receiver cores have been synthesized using Xilinx Vivado software. The cores have been targeted to Kintex7 XC7K410T-2 FFG900 device with a default balanced optimization strategy between area and timing. The area and performance metrics produced are summarized in the following tables.

DescriptionDVB-S2 BCH Encoder 9//bits IODVB-S2 LDPC Encoder 9//bits IODVB-S2 BCH Decoder 9//bits IO
FF996 (0.20%)3348 (0.68%)2430 (0.48%)
LUT1433 (0.56%)5234 (2.06%)14292 (5.62%)
BRAM0 (0.00%)25 (3.14%)2.5 (0.31%)
MHz250 MHz180 MHz120 MHz

DescriptionDVB-S2 LDPC L-min2 Decoder 9//LLRs IO S4.0 S8.2 360//DPUsDVB-S2 LDPC L-min2 Decoder 9//LLRs IO S4.0 S8.2 180//DPUsDVB-S2 LDPC L-min2 Decoder 9//LLRs IO S5.0 S9.2 180//DPUs
FF49844 (9.80%)31106 (6.12%)34699 (6.82%)
LUT89416 (35.18%)59958 (23.59%)65581 (31.89%)
BRAM205 (25.79%)265.5 (33.40%)298 (37.48%)
MHz125 MHz125 MHz125 MHz

In ntDVBS2_FEC IP Core product brief we present performance metrics of BER vs. ES/N0, throughput rates and relative average iterations for QPSK modulation as measured in real-time using Noesis ComLab SW platform running at Kintex7 FPGA. All IPs have a 9-bit parallel IO interface. Specifically, for LDPC Decoder IP, various tradeoff versions are being presented. In terms of fixed point (FI) precision, S4.0 -S8.2(internal-external FI) and S5.0-S9.2 are being compared. In terms of internal datapath units (DPU) parallelism, a 360// DPU version is compared against the 180// DPU version. The 180// DPU trade-off version performs exactly like the 360//, but achieves half the throughput rate.

Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntDVBS2_FEC cores are available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:

  • Fully commented synthesizable VHDL source code or FPGA netlist
  • VHDL test bench and example configuration files.
  • MATLAB model.
  • Comprehensive technical documentation.
  • Technical support.

We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.

Contact us to request further IP Core product information.