Voice & Data Compression
A/u law 64 kbps Codec - ntG711
The ntG711 IP Core is comprised of the G711 compressor (ntG711_CMP) and the G711 expander (ntG711_EXP). The ntG711_CMP core implements the ITU G.711 compliant compressing. The G.711 standard specifies a compressing function for 16-bit uniform PCM to 8-bit A/μ-law word. The ntG711_EXP core implements the ITU G.711 compliant expanding. The G.711 standard specifies a translation for 8-bit A/μ-law in 14 -bit uniform PCM word. The ntG711_CMP and ntG711_EXP cores are programmable and their functionality is controlled by the following control bits.
law : This bit selects the coding rule to be used. When ‘0’ μ-law is selected, when ‘1’ A-law is selected.
A_inv_dis : This bit activates/disactivates the inversion of even bits of the output word for the A-law case.
u_inv_dis : This bit activates/disactivates the inversion of bits of the output word for the μ-law case.
comp_dis : This bit selects the representation format of the output vector. When ‘0’ is in 2’s complement format, when ‘1’ is in sign magnitude format.
The ntG711 core can be used in a variety of applications, including PCM codecs, voice companding and front–end for any DSP processing of 64 kbps voice.
● Expands 8 bit a-law or μ-law logarithmic PCM to 13/14 bit linear PCM.
● Compresses 16 bit linear PCM to 8 bit α-law or μ-law logarithmic PCM.
● Compliant to the ITU-G.711 standard.
● Purely combinational logic RTL implementation.
● Silicon proven in ASIC and FPGA technologies for a variety of applications.
The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements.
| Silicon Vendor | Device | Resources | Fmax (MHz) |
|---|---|---|---|
| AMD (Xilinx) | Kintex UltraScale+ | 130 CLB Slices / 1 DSP48 E | 350 |
| Microchip | PolarFire | 50 | |
| Lattice | Avant-X | 88 |
|
| Intel (Altera) | Agile 9 | ||
| TSMC | 0.18 um | 1330 gates | 200 |
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntG711 core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- C++ model.
- Comprehensive technical documentation.
- Technical support.
We offer IP Core characterizations for various FPGA technologies and ASIC process nodes. Click the links below to download respective product briefs:
AMD (Xilinx)
Microchip
Lattice
Intel (Altera)
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.
