Low Density Parity Check (LDPC) Codes
IEEE 802.11 n/ac/ac LDPC Encoder - ntLDPCE_80211
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_80211 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_80211 encoder IP (Figure) implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The ntLDPC_80211 cores can be used in a variety of applications, including:
- IEEE 802.11 n/ac/ax Wi-Fi 4, 5 or 6 standard compliant cases.
- Custom state-of-the-art systems for efficient high throughput FEC protection in both wire-line or wireless types of applications.
- Encoder supporting all IEEE 802.11 n/ac/ax defined block lengths (648, 1296, 1944) and code rates (1/2, 2/3, 3/4 and 5/6).
- 27-Bit or 81-Bit encoder input/output interface wrappers, supporting AXI4 Lite bus protocol.
- Generic selection of multiple encoder instances under the same top level IO interface for seamless throughput increase.
- Peak data rate > 4Gbps, measured on Xilinx RFSoC FPGA, with ~10% device utilization. Higher rates achievable for FPGA or ASIC technologies.
- Synchronous single clock design.
- Silicon proven in ASIC and Xilinx FPGA implementation technologies.
The ntLDPC_80211 encoder core has been synthesized using Xilinx Vivado software. The core has been targeted to Ultra Scale RFSoC xczu28dr-ffvg1517-2-e FPGA device with a default balanced optimization strategy between area and timing. The area and performance metrics produced are summarized in the following tables.
| Description | Encoder P=81// IF 1x processing IP | Encoder P=27// IF 1x processing IP | Encoder P=81// IF 2x processing IP | Encoder P=81// IF 3x processing IP |
|---|---|---|---|---|
| FF | 542 (0.06%) | 673 (0.08%) | 1076 (0.13%) | 1597 (0.19%) |
| LUT | 1407 (0.33%) | 1382 (0.32%) | 2913 (0.68%) | 4481 (1.05%) |
| BRAM | 4.5 (0.42%) | 5.5 (0.51%) | 9 (1.13%) | 13.5 (1.25%) |
| MHz | 425 MHz | 425 MHz | 425 MHz | 425 MHz |
| Min-Max Throughput | 1.1 Gbps (1/2 648) - 5.93 Gbps (5/6 1944) | 1.1 Gbps (1/2 648) - 5.93 Gbps (5/6 1944) | 2.2 Gbps (1/2 648) - 11.89 Gbps (5/6 1944) | 3.3 Gbps (1/2 648) - 17.84 Gbps (5/6 1944) |
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores
into our client’s product.
Various licensing models are available. The ntLDPC_80211 core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies).
The following deliverables are included:
- Fully commented synthesizable VHDL source code or FPGA netlist.
- VHDL test bench and example configuration files.
- MATLAB model.
- Comprehensive technical documentation.
- Technical support.
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.
