Voice & Data Compression
ADPCM 16/24/32/40 kbps Codec- ntG726
The ntADPCM core is fully compliant with G.726 standard and supports up to 64 full duplex voice channels. The G.726 recommendations specifies the conversion of a 64 kbps A-law or μ-law pulse code modulation (PCM) to and from a 40, 32, 24 and 16 kbps channel. This conversion is applied to the PCM bit stream using an ADPCM transcoding technique. The ntADPCM core can be configured ‘on-the-fly’ for A-law or μ-law linear code and conversion rate on a per channel basis.
The core is used in applications that require reduction in transport and storage bandwidth requirements. It significantly offloads CPU tasks as a co-processing system element.
The ntADPCM core can be used in a variety of applications, including:
- Cordless handsets and base stations (DECT, CT2, Cellular).
- Integrated Access Devices.
- PBX’s (Private Branch Exchange).
- Voice storage, voice mail, WAN voice processing.
- DCME (ITU G.763).
- Variable bandwidth channel.
- DSL modem, Cable modem, DSLAM.
- Compliant with ITU G.721, G.723, G.726 and G.726-Annex recommendations.
- ‘On-the-fly’ configuration for variable compression rate, PCM law.
- Process capability of up to 64 full duplex or up to 128 half duplex voice channels.
- Burst and continuous mode support.
- No register based configuration is required.
- A-law, μ-law linear code format selection.
The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements..
|Xilinx||Virtex–II||2515 CLB Slices||60|
|TSMC||0.18 um||24K gates||200|
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client‟s engineering teams and to facilitate the integration of our IP cores into our client‟s product. Various licensing models are available. The ntADPCM core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- C source code.
- Comprehensive technical documentation.
- Technical support.
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.