Security
AES Low Power Cipher - ntAES8
ntAES8 core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key. The ntAES8 has been carefully designed to require minimum logic resources rendering it an ideal solution for low power applications. This has been achieved by using an 8-bit data path size which means that 16 clock cycles are required to load/unload the 128-bit plaintext/ciphertext block. The encryptor receives the 128-bit plaintext block in 8-bit input symbols and generates the corresponding 128-bit ciphertext block in 8-bit output symbols using a supplied 128, 192, or 256-bit AES key. The pre-computed key values are read from an internal round key RAM. A key expander module is provided as an optional module to allow automatic generation and loading of the round key RAM. The decryptor implements the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications.
The ntAES8 core can be used in a variety of applications, including:
- Electronic financial transactions. eCommerce, Banking, Securities exchange, Point-of-Sale
- Secure communications. Storage Area Networks (SAN), Virtual Private Networks (VPN), Video Conferencing, Voice services.
- Secure environments. Satellite communications, Surveillance systems, Network appliances.
- Personal mobile communications. Video phones, PDA, Point-to-Point Wireless
- Compliant to Advanced Encryption Standard (AES) (FIPS PUB 197).
- Supports both encryption and decryption functions.
- Supports 128/192/256-bit Cipher keys.
- Processes an 128-bit block in 480/582/684 clock cycles for 128/192/256-bits cipher keys respectively.
- Supports ECB, CBC, CFB, OFB and CTR modes.
- Optional Key Expansion module.
- Supports I/O data flow control capability.
- Exhibits highly optimized performance-silicon area ratio.
- Ideal for low-power applications.
- Fully synchronous design.
- Silicon proven in ASIC and FPGA technologies for a variety of applications.
The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements..
| Silicon Vendor | Device | Resources | Fmax (MHz) |
|---|---|---|---|
| Xilinx | Spartan 3 | 160 CLB Slices / 1 Block RAM | 200 |
| TSMC | 0.18 um | 1226 gates / 7680 RAM bits | 515 |
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntAES8 core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- C++ model.
- Comprehensive technical documentation.
- Technical support.
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.
