Voice & Data Compression
CS-ACELP 8 kbps Codec - ntG729
The growth in wireless communication systems, cellular mobile radio and VoIP technology has created the imperative need for bandwidth efficient, high speed quality voice coding algorithms. The ITU-T G.729 CS-ACELP is a high speech quality, low-bit rate (8kbps) codec that has been proposed to meet the voice compression requirements of a modern communication system.
However the real time SW implementation of a multi-channel ITU-T G.729 compliant voice codec in conventional DSP processors is prohibitive due to the intensive amount of signal processing power required by the algorithm. To overcome this limitation Noesis Technologies has developed a revolutionized, highly efficient hybrid architecture that implements real time multi-channel G729A voice coding and exhibits the best performance-silicon area ratio available in the industry. The ntG729 IP Core can be used as a coprocessor to any processor type and can save significant computing resources for the main processor by efficiently executing the computationally intensive speech coding G729A algorithmic operations.
The ntG729 core can be used in a variety of applications, including:
- Audio Conferencing Systems.
- Access Network Devices.
- IP Phones.
- Tele-presence Systems.
- VoIP Gateways.
- IP/PBXs.
- Voice Processors.
- Voice codec capable of multi-channel 8kbps voice compression based on ITU-T G729A standard.
- Selective Channel initialization.
- AMBA bus support for easy SoC integration.
- Best performance/silicon area ratio available in the industry.
- Fully synchronous design, using single clock.
- Portable to any FPGA/ASIC technology.
The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements..
| Silicon Vendor | Device | Resources | Fmax (MHz) |
|---|---|---|---|
| Xilinx | Virtex 7 | 18K CLB Slices / 31 Block RAMs / 105 DSP Slices | 117 |
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntG729 core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA or ASIC technologies). The following deliverables are included:
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- C++ model.
- Comprehensive technical documentation.
- Technical support.
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.
