Convolutional Turbo Codes (CTCs)
HomePlug AV2 CTC Decoder - ntCTCD
Description from product sheet
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Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntRSE core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- C++ model.
- Comprehensive technical documentation.
- Technical support.
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.