Networking

E2-E3 Framer/Deframer ntE2_E3

Noesis Technologies ntE2_E3 Framer/Deframer is designed for E2/E3 networks and supports all requirements of ITU recommendations G.742, G.751 and G.775. The core provides all the necessary data formatting transforms for transmission over E2/E3 networks. The device can by controlled through a simple set of dedicated ports, allowing robust operation. One ntE2_E3 core instance can operate either as an E1/E2 (2.048/8.448 Mbps) rate Multiplexer/Demultiplexer, or as an E2/E3 (8.448/34.368 Mbps) rate Multiplexer/Demultiplexer. In addition five ntE2_E3 cores can be instantiated to operate as an E1/E3 (2.048/34.368 Mbps) rate Multiplexer/Demultiplexer. The transmit side of the framer generates framing patterns, transmits the alarm and the national bits, interleaves the four tributaries into the high level data stream, calculates the justification mechanism status and the nature of the stuffing bits available, as well as generates alarms, status bits, and clock outputs. The receive side establishes frame synchronization, extracts the interleaved data, the alarm and national bits as well as the auxiliary channels data, monitors for error conditions and generates alarm flags, data valid bits, status bits and clock outputs. The HDB3 codecs can be either used or bypassed, on both transmit and receive sides, depending on the application. Finally both local and remote loopback features are available.

The ntE2_E3 core can be used in secondary or ternary rate digital trunk interfaces, computer to PBX interfaces (CPI and DMI), to any high speed computer-to-computer data link and generally, to any digital cross connect interface.

  • E2/E3 framer/deframer compliant to G.742, G.751, G.775 ITU-T standards.
  • Performs four E1 to one E2 or four E2 to one E3 multiplexing and vice-versa demultiplexing.
  • Five ntE2_E3 cascaded cores implement a sixteen E1 to one E3 Multilpexer/Demultilpexer.
  • Optional HDB3 Line Codecs one both Receive and Transmit sides.
  • Local and Remote Loop-back modes.
  • Configurable Frame Alignment Signal.
  • User access to the Alarm bit and the National bit.
  • User access to four low speed Auxiliary Channels, one per multiplexed tributary, available via unused stuffing bits.
  • Fully synchronous and parametric design.
  • Silicon proven in ASIC and FPGA technologies for a variety of applications.

The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements..

Silicon VendorDeviceResourcesFmax
(MHz)
XilinxVirtex 6436 Slices170 (clk_tx)
250 (clk_rx)
XilinxVirtex 6406 Slices186 (clk_tx)
205 (clk_rx)
AlteraEP4CGX301816 LEs143 (clk_tx)
198 (clk_rx)
AlteraEP4CGX301807 LEs136 (clk_tx)
193 (clk_rx)

Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntE2_E3 core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:

  • Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
  • VHDL or Verilog test benches and example configuration files.
  • Comprehensive technical documentation.
  • Technical support.

We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.

Contact us to request further IP Core product information.