Voice & Data Compression
Huffman compression engine - ntHUFF
The ntHUFF compression module implements the Huffman Block differential compression algorithm. The core processes data blocks of 500 16-bit input samples “on the fly” with latency as little as 4 clock cycles. A small input buffer of configurable size stores incoming 16-bit samples and propagates them to the compression module when instructed by the local controller. Samples are propagated through the differential data path comprised of a subtractor and an absolute calculation unit. The absolute value of all samples is used to update a metric table with statistical information and is also used to produce the compressed output. This is the initialization phase of the system. When samples equal to the defined block size have been collected, the controller enters calculations phase and pauses further samples propagation to the rest of the system. The Huffman microprocessor unit calculates and produces the Huffman (S) table, based on the populated metric table, which will be applied on the next block of incoming data. The custom microprocessor functions with encoded operations designed to optimize this phase. The core of the Huffman algorithm is implemented by performing parallel memory accesses on a parallel memory.
A 512×36 instruction memory drives the microprocessor to execute all real time Huffman algorithm calculations. Worst case processing latency due to iterative algorithm nature is calculated to 4175 clock cycles per block of 500 samples. Once the Huffman (S) table has been calculated, the controller resumes samples propagation through the differential data path and S is applied to the next block of incoming samples in order to produce the compressed output. When samples equal to the defined block size have been collected, the calculations phase is activated again and so on. A flush enable input port is provided, which applies zero padding on the last 32bit compressed output at the end of each data block.
- Wireless sensor networks.
- Medical applications.
- Any data compression application with slow changing nature of data, to fully benefit from the differential nature of the algorithm.
- Huffman block differential compression algorithm implementation.
- High compression rates for data flows nature appropriate for differential compression.
- Supports 16bit raw data input and produces 32bit compressed data output, with configurable endianness.
- Configurable input buffer characteristics to support required input data rates.
- Implements a custom processor, executing the Huffman block compression algorithm.
- Single interrupt “Ready for Data” pin, for robust environment interaction.
- Fully synchronous design, using single clock.
- Low power.
- High throughput rate performance.
- Portable to any FPGA/ASIC technology.
The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements..
| Silicon Vendor | Device | Resources | Fmax(MHz) |
|---|---|---|---|
| Xilinx | Spartan 3 | 1724 CLB Slices / 8 Block RAMs | 63 |
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntCVSD core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA or ASIC technologies). The following deliverables are included:
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- Matlab model.
- Comprehensive technical documentation.
- Technical support.
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.
