Baseband PHYs

OFDM Baseband Processor - ntOFDM_BBP

Noesis Technologies ntOFDM_BBP is a custom baseband processor, which implements the physical layer of an OFDM, time division duplexing (TDD) system. The baseband processor includes both transmission and reception bit-level and symbol-level processing chains including a sophisticated synchronization unit. The host interface is based on an AXI4 stream protocol. This high performance
OFDM transmission system is fully compliant with 802.16d (WiMAX) standard and is fully configurable via the integrated register file. An RF interface module is also included, compatible with Analog Devices AD9361 RF transceiver. Other RF interfaces can be supported. The Bit-level processing block (BLPB) transmission chain implements the following functional units : randomization, FEC encoding, interleaving and symbol mapping.

In BLPB reception chain the following operations are implemented: soft symbol demapping, deinterleaving, FEC decoding and de-randomization. The FEC module implements a powerful error correction scheme based on a concatenation of Reed Solomon—Viterbi algorithms. The Symbol-level processing block (SLPB) transmission chain implements the following functional units: OFDM symbol transmitter, IFFT, CP insertion. In reception chain the SLPB module is preceded by the synchronization unit, which is searching for known preamble values in order to locate the start an incoming WiMAX sub-frame. Once the sub-frame is located, frequency offset compensation is applied and received information is propagated down to SLPB reception chain. In SLPB reception chain the following operations take place: CP removal, FFT, OFDM symbol receiver, channel estimation, phase offset compensation and channel equalization.

The ntOFDM_BBP core implements a performance optimized, OFDM, TDD based baseband processor which can be used in a variety of wireless broadband applications.

  • Customized transmit and receive physical layer chains.
  • Fully synchronous design enabling high throughput TDD operation.
  • BLPB and SLPB processing blocks.
  • Implements a sophisticated synchronization algorithm to efficiently detect and isolate received modulated payload information.
  • Configurable as either downlink (DL) baseband station or uplink (UL) baseband station.
  • Configurable data randomization, modulation level and code rate.
  • Host interface based on AXI4 stream protocol.
  • RF interfacing supporting Analog Devices AD9361 RF Transceiver.
  • Fully synchronous design.
  • Silicon proven in FPGA technologies.

The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements..

Silicon VendorDeviceResources
XilinxKintex-724763 Slices /
294 DSP48 /
128 Block RAMs

Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntOFDM_BBP core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:

  • Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
  • VHDL or Verilog test benches and example configuration files.
  • Comprehensive technical documentation.
  • Technical support.

We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.

Contact us to request further IP Core product information.