Security
SHA 256-bit Hash Generator - ntSHA256
An n-bit hash is a map from arbitrary length messages to n-bit hash values. An n-bit cryptographic hash is an n-bit hash which is one-way and collision-resistant. Such functions are important cryptographic primitives used for such things as digital signatures and password protection. Current popular hashes produce hash values of length n = 128 (MD4 and MD5) and n = 160 (SHA-1), and therefore can provide no more than 64 or 80 bits of security, respectively, against collision attacks. Since the goal of the new Advanced Encryption Standard (AES) is to offer, at its three cryptovariable sizes, 128, 192, and 256 bits of security, there is a need for companion hash algorithms which provide similar levels of enhanced security. ntSHA256 IP Core implements SHA-256, or Secure Hash Algorithm-256 which is one of the latest hash functions standardized by the U.S. Federal Government. It is a 256-bit hash and is meant to provide 128 bits of security against collision attacks. The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications.
The ntSHA256 core can be used in a variety of applications, including:
- Security applications and protocols (TLS, PGP, SSH, S/MIME, IPsec).
- Authentication of Debian GNU/Linux software packages.
- DKIM message signing standard.
- Transaction verification and proof-of-work calculation for several crypto-currencies (Bitcoin).
- Password protection.
- Digital signatures.
- Message authentication.
- Data integrity check.
- Compliant to FIPS 180-2 specification of SHA-256.
- Internally implemented bit padding unit.
- Supports input message length multiple of 8-bit.
- Parametric hash values (h) of Chaining Variables.
- Parametric SHA256 constant values table (k).
- 66 processing cycles per 512-bit message block.
- Simple interface.
- Fully synchronous design.
- Silicon proven in ASIC and FPGA technologies for a variety of applications.
The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements..
| Silicon Vendor | Device | Resources | Fmax (MHz) |
|---|---|---|---|
| Xilinx | Spartan 3A | 1577 CLB Slices / 1 Block RAM | 50 |
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntSHA256 core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- Comprehensive technical documentation.
- Technical support.
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.
