Baseband PHYs
Smart Grid PLC Baseband Processor - ntG3_BBP
The ntG3_BBP is a fully compliant ITU-T G.9903 baseband modem that can be used in a wide range of smart grid applications over power lines, including smart metering and energy management in energy generation and distribution systems, lighting and industrial automation as well as automotive EV charging. The ntG3_BBP IP core main functional blocks are the transmitter, the receiver, the register file, the AHB-Lite wrapper and the analog front end interface. The user accesses the core via the AHB interface to either program the register file or provide payload data to the core. By programming the register file the user sets a specific functional mode of operation, requests the ntG3_BBP to transmit a data or acknowledgement PHY frame or accesses remotely received control information.
The ntG3_BBP core can be used in a variety of applications, including:
- Smart Grids / Smart Cities.
- Smart Metering.
- Energy Management.
- Industrial Automation.
- Automotive EV Charging.
- PLC G3 physical layer (PHY) compliant baseband processor as per ITU-T G.9903 Chapter 7 and ITU-T G.9901 Annex B.
- CENELEC-A/B (3-148.5kHz) and FCC (9-490kHz) band plans support.
- Aware of basic MAC layer handshaking primitives.
- Data rates from a few kbps up to 290kbps.
- On the fly programmable control profile selection.
- Patent pending DSP techniques enable superior BER vs SNR performance.
- Compliant with AMBA AHB-Lite or AXI-4 protocol.
- Synchronous clock design.
- Silicon proven in Xilinx FPGA implementation technologies.
- Pending G3-PLC Alliance platform certification.
The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements..
| Silicon Vendor | Device | Resources | Fmax (MHz) |
|---|---|---|---|
| Xilinx | Kintex-7 | Transmitter: 6275 CLB Slices / 46 Block RAMs / 57 DSP48s | 156 |
| Xilinx | Kintex-7 | Receiver: 14588 CLB Slices / 61 Block RAMs / 91 DSP48s | 74 |
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntG3_BBP core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- Matlab model in mex format.
- Comprehensive technical documentation.
- Technical support.
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.
