Telecom DSP

Time & Frequency Synchronizer - ntSYNC

Noesis Technologies ntSYNC is a fully programmable component used to achieve time and frequency synchronization in OFDM technology physical layer implementations. It interfaces directly with the physical layer’s front-end (line/RF) interface and using a cross-correlation proprietary algorithm to find the starting point of a received data frame. The generic design approach as well as a number of pre-processed optimizations allow for integration to any OFDM compliant physical layer.
The front-end interface feeds the ntSYNC with received signal above a certain power level via the DINI/DINQ ports and flags the signal as valid (DRS). The signal is buffered temporarily in Raw Buffer until raw synchronization phase takes place. The raw synchronization algorithm searches for received power level equal to the a-priori known preamble power levels. The power levels can be programmed via the PWR_THRES input port.

Once raw synchronization is achieved the estimated location of the preamble is decided and the coarse synchronization phase begins. Coarse synchronization searches the preamble estimated location more closely with correlative metrics, approximates the received frames starting point and calculates the channels frequency offset shift on the received signal. The raw buffer discards data before the approximated synchronization point and propagates the rest of the signal to the frequency offset compensation unit. The results are being stored in the fine buffer. Additionally the estimated preamble data are being isolated.
The isolated preamble is correlated against the known generated preamble by the fine synchronization process. Fine synchronization decides the final synchronization point and discards all previous data in the fine buffer. The programmable OFDM control parameters such as cyclic prefix size (CP), sub-channelization operation (SUBCI), the size of the OFDM symbol (OFDM_SIZE) and the number of OFDM symbols that are expected to be included in the received frame (OFDM_NUM) are required in order to decide the end of the received frame, once the synchronization point has been calculated.

The ntSYNC core can be used for synchronization of wireless OFDM baseband modems.

  • Fully configurable, high throughput, OFDM synchronization unit.
  • Programmable cyclic prefix, sub-channelization index.
  • Based on a proprietary modification of Schmidl-Cox synchronization algorithm.
  • Programmable OFDM frame size and number of OFDM symbols per frame.
  • Fully synchronous design, using single clock.
  • Silicon proven in ASIC and FPGA technologies for a variety of applications.

The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements..

Silicon VendorDeviceResourcesFmax (MHz)
XilinxKintex-75314 CLB Slices /
27 Block RAMs /
96 DSP48 Blocks
86(CLK)
102(CLKX2)

Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntSYNC core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:

  • Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
  • VHDL or Verilog test benches and example configuration files.
  • Matlab model.
  • Comprehensive technical documentation.
  • Technical support.

We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.

Contact us to request further IP Core product information.