High Level Data Link Controller - ntHDLC
Noesis Technologies ntHDLC single channel High-Level Data Link Controller (HDLC) is a full-duplex transceiver with independent transmit and receive units for synchronous framing bit-level HDLC protocol operations. The ntHDLC can handle interframe and delimiting flags, frame check sequence based on CCITT CRC16/CRC32 polynomial, normal or transparent transmission modes, abort generation and detection. The system interface is very flexible and can be adapted towards FIFO, uP, or DMA controllers. The transmit and receive units and their associated control and status logic are independent. This partitioning strategy enables the Tx and Rx units to be instantiated in different place and/or level of the design hierarchy. Each unit (Tx, Rx and back-end interface) has its own clock domain with synchronous clock enable. Communication between the various clock domains is achieved via synchronization logic blocks.
The ntHDLC core can be used in a variety of applications, including:
- Embedded applications in Telecom systems.
- X.25 (LAPB), Q.921(LAPD) applications.
- Point to point communication links.
- ISDN, Q.922 Frame Relay, PBX, WAN.
- Single port synchronous serial line interface.
- Flag/Abort Generation/Detection.
- Zero Insertion/Deletion.
- Non-octet alignment detection.
- CCITT CRC-16 Generation and Checking.
- NRZ/NRZI encoding/decoding.
- Transparent mode support.
- Receive FIFO overrun detection.
- Transmit FIFO underrun detection.
- Frame status and frame length indicators.
- Runt frame detection.
- Separate clocks for Tx and RX interfaces.
- Supports fllag in interframe-time fill.
- 8-bit parallel back-end interface.
- Fully synchronous design.
- Silicon proven in ASIC and FPGA technologies for a variety of applications.
The core has been targeted to both ASIC and FPGA technologies for various applications. Noesis Technologies can also deliver netlist versions of the core optimized to specific area resources and performance requirements..
|Xilinx||Spartan 3||460 CLB Slices /|
10 Block RAMs
|Xilinx||Virtex 5||200 CLB Slices /|
10 Block RAMs
|Altera||Stratix-III||600 ALUTs /|
10 M9K RAM blocks
|TSMC||0.18 um||5800 gates /|
74 K RAM bits
Noesis has engaged an “open” licensing philosophy in order to allow maximum technology transfer to our client’s engineering teams and to facilitate the integration of our IP cores into our client’s product. Various licensing models are available. The ntHDLC core is available as a soft core (synthesizable HDL) or as a firm core (netlist for FPGA technologies). The following deliverables are included:
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configuration files.
- Comprehensive technical documentation.
- Technical support.
We offer a variety of IP Core evaluation options such as C++, Matlab bit-true reference models, encrypted RTL simulation models with standalone, self-checking, fully automated RTL test benches, time limited FPGA netlists as well as FPGA demo boards for real-time verification.