Job Title: Senior RTL Design Engineer – Telecom
Location: Patras / Greece
Job Type: Full-Time
About the Role:
Noesis Technologies is a leading IP Core provider excelling in the innovative design of hardware accelerated, reconfigurable, physical layer (PHY) baseband processors for communication technology. Our IP solutions are key components to the most sophisticated telecom systems and are technology enablers in the development of high quality end-products in emerging markets of IoT, Smart Home / Grid, Wireless Sensor Networks, Security, Defense, Automotive, Consumer Electronics as well as other application fields.
We are seeking a highly skilled, motivated, proactive Senior RTL Design Engineer to join our dynamic hardware engineering team, focusing on cutting-edge telecommunications systems. As a logic design engineer, you will be involved in all aspects of the design, from feasibility study, architectural definition, RTL design and verification up to silicon (FPGA or ASIC) bring-up and performance characterization, contributing to the development of next-generation telecom products.
Responsibilities:
- Design and develop RTL for high-speed digital blocks using VHDL/Verilog/SystemVerilog, assertion writing.
- Design of state machines, data paths, clock domain crossing logic, parameterized architectures.
- Conduct logic FPGA/ASIC Logic synthesis, linting, CDC analysis, and timing closure.
- Drive functional and formal verification in collaboration with verification engineers.
- RTL/Gate level verification, writing self-checking, automated test benches.
- Optimize designs for power, area, and performance.
- Support bring-up and validation on FPGA/emulation platforms.
- Contribute to design documentation and design reviews.
Key Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of experience in RTL design for complex digital systems.
- Strong knowledge of VHDL/Verilog/SystemVerilog and RTL design best practices.
- Experience with synthesis tools (Synopsys, Cadence, etc.) and timing analysis (STA).
- Solid understanding of SoC/ASIC design flow.
- Experience in telecom or networking domains preferred.
- Strong problem-solving and communication skills.
Bonus Points For:
- Exposure to DSP algorithms and fixed-point arithmetic.
- Experience in MATLAB, C/C++, and or Python.
- Experience in MATLAB/Simulink modelling of telecom algorithms.
- Knowledge of protocols like 5GNR, LTE, WiFi, Bluetooth or other wireless/wireline standards.
- Experience in building and implementing system-level procedures and algorithms.
- Understanding of modem designs, PHY DSP algorithms and hardware architectures.
- Experience with FPGA prototyping (Xilinx/Intel).
- Familiarity with version control systems and scripting languages (Python, Tcl, etc.).
- High level of self-motivation and desire to be challenged and learn new skills.
- Strong problem solving skills with high attention to detail.
What We Offer:
- Competitive compensation and benefits.
- Opportunity to work on state-of-the-art telecom solutions.
- Dynamic, collaborative, and innovative work environment.
- Career growth and mentorship from industry leaders.
- Participate in large exhibitions around the world.
The candidate will join our team in our RnD center, in Patras Science Park, Patras, Greece. If you believe that you want to join our company, please forward your CV to info@noesis-tech.com
(Reference number: Sr_RTL_03)
